Integrated circuits have become more “dense” over time, i.e., more logic features have been implemented in an IC of a given size. Unfortunately, having all components on a single die IC has become problematic. Fortunately, multiple die may be stacked to provide a stacked die IC (“stacked die”). Such stacked ide may allow for lower power consumption, less current leakage, greater performance, and/or smaller IC size, among other benefits, as compared with trying to form a comparable single die IC. However, by attaching one or more integrated circuit dies to an interposer to form a stacked die, there are risks of damage associated to such one or more integrated circuit dies which are not present in formation of a single die IC. These damage risks may reduce yield and/or reliability of stacked dies.
Hence, it is desirable and useful to mitigate one or more of such risks of damage to increase stacked die yield and/or reliability.